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Quantum Paper Club

Performance constraints of NISQ quantum algorithms and their mitigation with 3D-integrated superconducting quantum devices

14.03.2024

17:45

HIT H42

14.03.2024

17:45

HIT H42

Presenter Photo

Kieran Dalton

Ph.D. student at ETH, Quantum Device Lab (QUDEV)

Abstract

In recent years, the excitement around NISQ algorithms has diminished, partly due to the performance limitations of existing quantum computers. Devices with more qubits and lower error rates are necessary to realize the potential of quantum computing.

In the first half of this talk, I will illustrate these performance limitations with the example of the variational quantum eigensolver (VQE). The VQE is a hybrid quantum-classical algorithm previously believed to be somewhat noise-resilient. However, leading VQE variants still require gate-error probabilities many orders of magnitude below those realized in the laboratory.  In the second half, I will discuss one of the ways in which these limitations are being addressed in superconducting circuits. Existing planar superconducting quantum devices face a scaling bottleneck due to wiring density and the crosstalk this provokes. To alleviate this, devices are being expanded into the third dimension, known as 3D-integration, for which flip-chip bonding is a leading enabling technology. As well as this, flip-chip bonding empowers the development of modular quantum devices consisting of a large carrier chip and smaller, application-specific and individually-inspected modules. This is likely to improve yield, and will provide a test-bed for distributed quantum computing.

References