Atomistic DFT Simulation of Scaled 3nm FinFET & 22nm FDSOI CMOS Quantum Dot Devices

Abstract

Current production FinFET and FDSOI CMOS technologies are suitable for large-scale, high-density quantum processor (QP) and readout control electronics. Due to layout manufacturability restrictions, that limit the types of qubit arrays and gates that can be implemented, the top gate pitch is too large for strong tunnel coupling between adjacent quantum dots (QDs), limiting the operation temperature and fidelity of two-spin swap gates. In production 22nm FDSOI CMOS, this can be overcome using a selective back-gate. I will present my work that explores this strategy using atomistic, DFT simulation by Synopsys’ Quantum-ATK, characterizing a scaled 22nm FDSOI double quantum dot (DQD) with selective backgate and 3nm FinFET QD at cryogenic temperatures. This study gains insight into the potential use of production FinFET and FDSOI devices for monolithic spin-qubit QPs operating above 2K.